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aAREA-power-delay-trade-off in logic synthesis.; by Michel R.C.M. Berkelaar
hBook
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a9090053328
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aBERKELAAR Michel R.C.M
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a20080105171509
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a
b[tp]
c0000
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a621.395 BER
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axvii, 117 hlm.
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cxvii, 117 hlm.; gamb., tab.;25 cm
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aBook